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<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Gowin Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>v1.8.0.02Beta</td>
</tr>
<tr>
<td class="label">Series, Device, Package, Speed, Operating Conditions</td>
<td>GW1N, GW1N-4, LQFP144, 6, COMMERCIAL</td>
</tr>
<tr>
<td class="label">Design Name</td>
<td>demo</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\fpga_led_tm1637\impl\synthesize\rev_1\fpga_led_tm1637.vm</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Timing Report File</td>
<td>C:\fpga_led_tm1637\impl\pnr\fpga_led_tm1637.tr.html</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Fri Oct 26 11:06:04 2018
</td>
</tr>
<tr>
<td class="label">Command Line</td>
<td>C:\Gowin\1.8\Pnr\bin\gowin.exe -do C:\fpga_led_tm1637\impl\pnr\cmd.do </td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2017 Gowin Semiconductor Corporation.                      All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 1.14V 85C</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 1.26V 0C</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>393</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>346</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>0</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
<tr>
<td>DEFAULT_CLK</td>
<td>Base</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Fmax</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>DEFAULT_CLK</td>
<td>124.715(MHz)</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
<tr>
<td>DEFAULT_CLK</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>DEFAULT_CLK</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>1.982</td>
<td>cnt_Z[19]/Q</td>
<td>cnt_Z[24]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>7.418</td>
</tr>
<tr>
<td>2</td>
<td>2.066</td>
<td>cnt_Z[3]/Q</td>
<td>cnt_Z[16]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>7.334</td>
</tr>
<tr>
<td>3</td>
<td>2.066</td>
<td>cnt_Z[3]/Q</td>
<td>cnt_Z[18]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>7.334</td>
</tr>
<tr>
<td>4</td>
<td>2.160</td>
<td>cnt_Z[3]/Q</td>
<td>cnt_Z[6]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>7.240</td>
</tr>
<tr>
<td>5</td>
<td>2.160</td>
<td>cnt_Z[3]/Q</td>
<td>cnt_Z[11]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>7.240</td>
</tr>
<tr>
<td>6</td>
<td>2.169</td>
<td>cnt_Z[3]/Q</td>
<td>cnt_Z[21]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>7.231</td>
</tr>
<tr>
<td>7</td>
<td>2.182</td>
<td>cnt_Z[19]/Q</td>
<td>cnt_Z[19]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>7.218</td>
</tr>
<tr>
<td>8</td>
<td>2.272</td>
<td>cnt_Z[19]/Q</td>
<td>cnt_Z[20]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>7.128</td>
</tr>
<tr>
<td>9</td>
<td>2.466</td>
<td>cnt_Z[19]/Q</td>
<td>cnt_Z[22]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.934</td>
</tr>
<tr>
<td>10</td>
<td>2.468</td>
<td>cnt_Z[6]/Q</td>
<td>cnt_Z[13]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.932</td>
</tr>
<tr>
<td>11</td>
<td>2.478</td>
<td>cnt_Z[3]/Q</td>
<td>cnt_Z[14]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.922</td>
</tr>
<tr>
<td>12</td>
<td>2.913</td>
<td>cnt_Z[19]/Q</td>
<td>cnt_Z[12]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.487</td>
</tr>
<tr>
<td>13</td>
<td>3.290</td>
<td>cnt_Z[3]/Q</td>
<td>clk_spi_Z/CE</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>6.466</td>
</tr>
<tr>
<td>14</td>
<td>5.130</td>
<td>cnt_Z[6]/Q</td>
<td>cnt_Z[23]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>4.270</td>
</tr>
<tr>
<td>15</td>
<td>5.472</td>
<td>cnt_Z[6]/Q</td>
<td>cnt_Z[17]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>3.928</td>
</tr>
<tr>
<td>16</td>
<td>5.586</td>
<td>cnt_Z[6]/Q</td>
<td>cnt_Z[15]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>3.814</td>
</tr>
<tr>
<td>17</td>
<td>5.871</td>
<td>cnt_Z[6]/Q</td>
<td>cnt_Z[10]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>3.529</td>
</tr>
<tr>
<td>18</td>
<td>5.928</td>
<td>cnt_Z[6]/Q</td>
<td>cnt_Z[9]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>3.472</td>
</tr>
<tr>
<td>19</td>
<td>5.985</td>
<td>cnt_Z[6]/Q</td>
<td>cnt_Z[8]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>3.415</td>
</tr>
<tr>
<td>20</td>
<td>6.042</td>
<td>cnt_Z[6]/Q</td>
<td>cnt_Z[7]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>3.358</td>
</tr>
<tr>
<td>21</td>
<td>6.818</td>
<td>cnt_Z[1]/Q</td>
<td>cnt_Z[5]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.582</td>
</tr>
<tr>
<td>22</td>
<td>6.875</td>
<td>cnt_Z[1]/Q</td>
<td>cnt_Z[4]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.525</td>
</tr>
<tr>
<td>23</td>
<td>6.932</td>
<td>cnt_Z[1]/Q</td>
<td>cnt_Z[3]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.468</td>
</tr>
<tr>
<td>24</td>
<td>6.987</td>
<td>cnt_Z[24]/Q</td>
<td>clk_spi_Z/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.413</td>
</tr>
<tr>
<td>25</td>
<td>6.989</td>
<td>cnt_Z[1]/Q</td>
<td>cnt_Z[2]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>2.411</td>
</tr>
</table>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.708</td>
<td>clk_spi_Z/Q</td>
<td>clk_spi_Z/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.708</td>
</tr>
<tr>
<td>2</td>
<td>0.711</td>
<td>cnt_Z[24]/Q</td>
<td>cnt_Z[24]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.711</td>
</tr>
<tr>
<td>3</td>
<td>0.853</td>
<td>cnt_Z[8]/Q</td>
<td>cnt_Z[8]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.853</td>
</tr>
<tr>
<td>4</td>
<td>0.853</td>
<td>cnt_Z[0]/Q</td>
<td>cnt_Z[0]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.853</td>
</tr>
<tr>
<td>5</td>
<td>0.853</td>
<td>cnt_Z[2]/Q</td>
<td>cnt_Z[2]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.853</td>
</tr>
<tr>
<td>6</td>
<td>0.964</td>
<td>cnt_Z[24]/Q</td>
<td>cnt_Z[20]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.964</td>
</tr>
<tr>
<td>7</td>
<td>0.964</td>
<td>cnt_Z[24]/Q</td>
<td>cnt_Z[22]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.964</td>
</tr>
<tr>
<td>8</td>
<td>1.085</td>
<td>cnt_Z[10]/Q</td>
<td>cnt_Z[10]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.085</td>
</tr>
<tr>
<td>9</td>
<td>1.085</td>
<td>cnt_Z[4]/Q</td>
<td>cnt_Z[4]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.085</td>
</tr>
<tr>
<td>10</td>
<td>1.088</td>
<td>cnt_Z[5]/Q</td>
<td>cnt_Z[5]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.088</td>
</tr>
<tr>
<td>11</td>
<td>1.088</td>
<td>cnt_Z[15]/Q</td>
<td>cnt_Z[15]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.088</td>
</tr>
<tr>
<td>12</td>
<td>1.088</td>
<td>cnt_Z[9]/Q</td>
<td>cnt_Z[9]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.088</td>
</tr>
<tr>
<td>13</td>
<td>1.088</td>
<td>cnt_Z[3]/Q</td>
<td>cnt_Z[3]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.088</td>
</tr>
<tr>
<td>14</td>
<td>1.093</td>
<td>cnt_Z[7]/Q</td>
<td>cnt_Z[7]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.093</td>
</tr>
<tr>
<td>15</td>
<td>1.093</td>
<td>cnt_Z[1]/Q</td>
<td>cnt_Z[1]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.093</td>
</tr>
<tr>
<td>16</td>
<td>1.094</td>
<td>cnt_Z[17]/Q</td>
<td>cnt_Z[17]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.094</td>
</tr>
<tr>
<td>17</td>
<td>1.098</td>
<td>cnt_Z[23]/Q</td>
<td>cnt_Z[23]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.098</td>
</tr>
<tr>
<td>18</td>
<td>1.134</td>
<td>cnt_Z[24]/Q</td>
<td>cnt_Z[19]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.134</td>
</tr>
<tr>
<td>19</td>
<td>1.250</td>
<td>cnt_Z[23]/Q</td>
<td>cnt_Z[12]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.250</td>
</tr>
<tr>
<td>20</td>
<td>1.724</td>
<td>cnt_Z[23]/Q</td>
<td>cnt_Z[14]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.724</td>
</tr>
<tr>
<td>21</td>
<td>1.806</td>
<td>cnt_Z[17]/Q</td>
<td>cnt_Z[21]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.806</td>
</tr>
<tr>
<td>22</td>
<td>1.806</td>
<td>cnt_Z[17]/Q</td>
<td>cnt_Z[16]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.806</td>
</tr>
<tr>
<td>23</td>
<td>1.806</td>
<td>cnt_Z[17]/Q</td>
<td>cnt_Z[18]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.806</td>
</tr>
<tr>
<td>24</td>
<td>1.901</td>
<td>cnt_Z[17]/Q</td>
<td>clk_spi_Z/CE</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.916</td>
</tr>
<tr>
<td>25</td>
<td>1.909</td>
<td>cnt_Z[24]/Q</td>
<td>cnt_Z[6]/D</td>
<td>DEFAULT_CLK:[R]</td>
<td>DEFAULT_CLK:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.909</td>
</tr>
</table>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>Nothing to report!</h4>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<tr>
<td>1</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>cnt_Z[4]</td>
</tr>
<tr>
<td>2</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>cnt_Z[2]</td>
</tr>
<tr>
<td>3</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>cnt_Z[18]</td>
</tr>
<tr>
<td>4</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>cnt_Z[10]</td>
</tr>
<tr>
<td>5</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>cnt_Z[11]</td>
</tr>
<tr>
<td>6</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>cnt_Z[19]</td>
</tr>
<tr>
<td>7</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>cnt_Z[12]</td>
</tr>
<tr>
<td>8</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>clk_spi_Z</td>
</tr>
<tr>
<td>9</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>cnt_Z[13]</td>
</tr>
<tr>
<td>10</td>
<td>2.329</td>
<td>3.579</td>
<td>1.250</td>
<td>Low Pulse Width</td>
<td>DEFAULT_CLK</td>
<td>cnt_Z[20]</td>
</tr>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.982</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.788</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[19]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[24]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[0][B]</td>
<td>cnt_Z[19]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R8C11[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[19]/Q</td>
</tr>
<tr>
<td>5.636</td>
<td>0.808</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[3][A]</td>
<td>un1_cntlto22_4_3_cZ/I1</td>
</tr>
<tr>
<td>6.668</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R9C12[3][A]</td>
<td style=" background: #97FFFF;">un1_cntlto22_4_3_cZ/F</td>
</tr>
<tr>
<td>7.503</td>
<td>0.835</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C12[1][B]</td>
<td>un1_cntlto24_d_0_cZ/I3</td>
</tr>
<tr>
<td>8.535</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>6</td>
<td>R11C12[1][B]</td>
<td style=" background: #97FFFF;">un1_cntlto24_d_0_cZ/F</td>
</tr>
<tr>
<td>8.551</td>
<td>0.016</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C12[2][B]</td>
<td>un1_cntlto24_d_cZ/I3</td>
</tr>
<tr>
<td>9.650</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R11C12[2][B]</td>
<td style=" background: #97FFFF;">un1_cntlto24_d_cZ/F</td>
</tr>
<tr>
<td>10.966</td>
<td>1.316</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C11[0][A]</td>
<td>cnt_RNO[24]/I3</td>
</tr>
<tr>
<td>11.788</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C11[0][A]</td>
<td style=" background: #97FFFF;">cnt_RNO[24]/F</td>
</tr>
<tr>
<td>11.788</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C11[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[24]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[0][A]</td>
<td>cnt_Z[24]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[24]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C11[0][A]</td>
<td>cnt_Z[24]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.985, 53.719%; route: 2.975, 40.103%; tC2Q: 0.458, 6.178%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.066</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.704</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[3]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[16]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[2][A]</td>
<td>cnt_Z[3]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C9[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[3]/Q</td>
</tr>
<tr>
<td>5.167</td>
<td>0.339</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C9[3][B]</td>
<td>un1_cntlto10_N_4L5_cZ/I1</td>
</tr>
<tr>
<td>6.228</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R9C9[3][B]</td>
<td style=" background: #97FFFF;">un1_cntlto10_N_4L5_cZ/F</td>
</tr>
<tr>
<td>6.647</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[3][A]</td>
<td>un1_cntlto10/I3</td>
</tr>
<tr>
<td>7.469</td>
<td>0.822</td>
<td>tINS</td>
<td>RF</td>
<td>3</td>
<td>R9C10[3][A]</td>
<td style=" background: #97FFFF;">un1_cntlto10/F</td>
</tr>
<tr>
<td>8.453</td>
<td>0.984</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C12[0][A]</td>
<td>un1_cntlto14/I0</td>
</tr>
<tr>
<td>9.275</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R11C12[0][A]</td>
<td style=" background: #97FFFF;">un1_cntlto14/F</td>
</tr>
<tr>
<td>10.605</td>
<td>1.330</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[1][A]</td>
<td>cnt_RNO[16]/I0</td>
</tr>
<tr>
<td>11.704</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C13[1][A]</td>
<td style=" background: #97FFFF;">cnt_RNO[16]/F</td>
</tr>
<tr>
<td>11.704</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[16]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C13[1][A]</td>
<td>cnt_Z[16]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[16]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C13[1][A]</td>
<td>cnt_Z[16]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.804, 51.870%; route: 3.071, 41.881%; tC2Q: 0.458, 6.250%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.066</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.704</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[3]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[18]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[2][A]</td>
<td>cnt_Z[3]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C9[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[3]/Q</td>
</tr>
<tr>
<td>5.167</td>
<td>0.339</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C9[3][B]</td>
<td>un1_cntlto10_N_4L5_cZ/I1</td>
</tr>
<tr>
<td>6.228</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R9C9[3][B]</td>
<td style=" background: #97FFFF;">un1_cntlto10_N_4L5_cZ/F</td>
</tr>
<tr>
<td>6.647</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[3][A]</td>
<td>un1_cntlto10/I3</td>
</tr>
<tr>
<td>7.469</td>
<td>0.822</td>
<td>tINS</td>
<td>RF</td>
<td>3</td>
<td>R9C10[3][A]</td>
<td style=" background: #97FFFF;">un1_cntlto10/F</td>
</tr>
<tr>
<td>8.453</td>
<td>0.984</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C12[0][A]</td>
<td>un1_cntlto14/I0</td>
</tr>
<tr>
<td>9.275</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R11C12[0][A]</td>
<td style=" background: #97FFFF;">un1_cntlto14/F</td>
</tr>
<tr>
<td>10.605</td>
<td>1.330</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[1][B]</td>
<td>cnt_RNO[18]/I0</td>
</tr>
<tr>
<td>11.704</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C13[1][B]</td>
<td style=" background: #97FFFF;">cnt_RNO[18]/F</td>
</tr>
<tr>
<td>11.704</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[1][B]</td>
<td style=" font-weight:bold;">cnt_Z[18]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C13[1][B]</td>
<td>cnt_Z[18]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[18]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C13[1][B]</td>
<td>cnt_Z[18]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.804, 51.870%; route: 3.071, 41.881%; tC2Q: 0.458, 6.250%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.160</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.610</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[3]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[6]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[2][A]</td>
<td>cnt_Z[3]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C9[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[3]/Q</td>
</tr>
<tr>
<td>5.167</td>
<td>0.339</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C9[3][B]</td>
<td>un1_cntlto10_N_4L5_cZ/I1</td>
</tr>
<tr>
<td>6.228</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R9C9[3][B]</td>
<td style=" background: #97FFFF;">un1_cntlto10_N_4L5_cZ/F</td>
</tr>
<tr>
<td>6.647</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[3][A]</td>
<td>un1_cntlto10/I3</td>
</tr>
<tr>
<td>7.469</td>
<td>0.822</td>
<td>tINS</td>
<td>RF</td>
<td>3</td>
<td>R9C10[3][A]</td>
<td style=" background: #97FFFF;">un1_cntlto10/F</td>
</tr>
<tr>
<td>8.453</td>
<td>0.984</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C12[3][A]</td>
<td>un1_cntlto17_0_0_1_cZ/I1</td>
</tr>
<tr>
<td>9.275</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R11C12[3][A]</td>
<td style=" background: #97FFFF;">un1_cntlto17_0_0_1_cZ/F</td>
</tr>
<tr>
<td>9.286</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C12[3][B]</td>
<td>un1_cntlto17_0_0/I1</td>
</tr>
<tr>
<td>10.088</td>
<td>0.802</td>
<td>tINS</td>
<td>FR</td>
<td>2</td>
<td>R11C12[3][B]</td>
<td style=" background: #97FFFF;">un1_cntlto17_0_0/F</td>
</tr>
<tr>
<td>10.511</td>
<td>0.423</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C13[0][B]</td>
<td>cnt_3_cZ[6]/I2</td>
</tr>
<tr>
<td>11.610</td>
<td>1.099</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R11C13[0][B]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[6]/F</td>
</tr>
<tr>
<td>11.610</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C13[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[6]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C13[0][B]</td>
<td>cnt_Z[6]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[6]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C13[0][B]</td>
<td>cnt_Z[6]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.606, 63.621%; route: 2.175, 30.048%; tC2Q: 0.458, 6.331%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.160</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.610</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[3]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[11]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[2][A]</td>
<td>cnt_Z[3]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C9[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[3]/Q</td>
</tr>
<tr>
<td>5.167</td>
<td>0.339</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C9[3][B]</td>
<td>un1_cntlto10_N_4L5_cZ/I1</td>
</tr>
<tr>
<td>6.228</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R9C9[3][B]</td>
<td style=" background: #97FFFF;">un1_cntlto10_N_4L5_cZ/F</td>
</tr>
<tr>
<td>6.647</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[3][A]</td>
<td>un1_cntlto10/I3</td>
</tr>
<tr>
<td>7.469</td>
<td>0.822</td>
<td>tINS</td>
<td>RF</td>
<td>3</td>
<td>R9C10[3][A]</td>
<td style=" background: #97FFFF;">un1_cntlto10/F</td>
</tr>
<tr>
<td>8.453</td>
<td>0.984</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C12[3][A]</td>
<td>un1_cntlto17_0_0_1_cZ/I1</td>
</tr>
<tr>
<td>9.275</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R11C12[3][A]</td>
<td style=" background: #97FFFF;">un1_cntlto17_0_0_1_cZ/F</td>
</tr>
<tr>
<td>9.286</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C12[3][B]</td>
<td>un1_cntlto17_0_0/I1</td>
</tr>
<tr>
<td>10.088</td>
<td>0.802</td>
<td>tINS</td>
<td>FR</td>
<td>2</td>
<td>R11C12[3][B]</td>
<td style=" background: #97FFFF;">un1_cntlto17_0_0/F</td>
</tr>
<tr>
<td>10.511</td>
<td>0.423</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C13[1][A]</td>
<td>cnt_3_cZ[11]/I2</td>
</tr>
<tr>
<td>11.610</td>
<td>1.099</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R11C13[1][A]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[11]/F</td>
</tr>
<tr>
<td>11.610</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C13[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[11]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C13[1][A]</td>
<td>cnt_Z[11]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[11]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C13[1][A]</td>
<td>cnt_Z[11]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.606, 63.621%; route: 2.175, 30.048%; tC2Q: 0.458, 6.331%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.169</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.601</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[3]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[21]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[2][A]</td>
<td>cnt_Z[3]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C9[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[3]/Q</td>
</tr>
<tr>
<td>5.167</td>
<td>0.339</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C9[3][B]</td>
<td>un1_cntlto10_N_4L5_cZ/I1</td>
</tr>
<tr>
<td>6.228</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R9C9[3][B]</td>
<td style=" background: #97FFFF;">un1_cntlto10_N_4L5_cZ/F</td>
</tr>
<tr>
<td>6.647</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[3][A]</td>
<td>un1_cntlto10/I3</td>
</tr>
<tr>
<td>7.469</td>
<td>0.822</td>
<td>tINS</td>
<td>RF</td>
<td>3</td>
<td>R9C10[3][A]</td>
<td style=" background: #97FFFF;">un1_cntlto10/F</td>
</tr>
<tr>
<td>8.453</td>
<td>0.984</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C12[0][A]</td>
<td>un1_cntlto14/I0</td>
</tr>
<tr>
<td>9.275</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R11C12[0][A]</td>
<td style=" background: #97FFFF;">un1_cntlto14/F</td>
</tr>
<tr>
<td>10.569</td>
<td>1.294</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[2][A]</td>
<td>cnt_RNO[21]/I0</td>
</tr>
<tr>
<td>11.601</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C13[2][A]</td>
<td style=" background: #97FFFF;">cnt_RNO[21]/F</td>
</tr>
<tr>
<td>11.601</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[21]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C13[2][A]</td>
<td>cnt_Z[21]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[21]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C13[2][A]</td>
<td>cnt_Z[21]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.737, 51.678%; route: 3.036, 41.984%; tC2Q: 0.458, 6.338%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.182</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.587</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[19]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[19]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[0][B]</td>
<td>cnt_Z[19]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R8C11[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[19]/Q</td>
</tr>
<tr>
<td>5.636</td>
<td>0.808</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[3][A]</td>
<td>un1_cntlto22_4_3_cZ/I1</td>
</tr>
<tr>
<td>6.668</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R9C12[3][A]</td>
<td style=" background: #97FFFF;">un1_cntlto22_4_3_cZ/F</td>
</tr>
<tr>
<td>7.503</td>
<td>0.835</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C12[1][B]</td>
<td>un1_cntlto24_d_0_cZ/I3</td>
</tr>
<tr>
<td>8.535</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>6</td>
<td>R11C12[1][B]</td>
<td style=" background: #97FFFF;">un1_cntlto24_d_0_cZ/F</td>
</tr>
<tr>
<td>8.551</td>
<td>0.016</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C12[2][B]</td>
<td>un1_cntlto24_d_cZ/I3</td>
</tr>
<tr>
<td>9.650</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R11C12[2][B]</td>
<td style=" background: #97FFFF;">un1_cntlto24_d_cZ/F</td>
</tr>
<tr>
<td>10.961</td>
<td>1.311</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C11[0][B]</td>
<td>cnt_RNO[19]/I3</td>
</tr>
<tr>
<td>11.587</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C11[0][B]</td>
<td style=" background: #97FFFF;">cnt_RNO[19]/F</td>
</tr>
<tr>
<td>11.587</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C11[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[19]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[0][B]</td>
<td>cnt_Z[19]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[19]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C11[0][B]</td>
<td>cnt_Z[19]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.789, 52.496%; route: 2.970, 41.154%; tC2Q: 0.458, 6.350%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.272</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.498</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[19]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[20]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[0][B]</td>
<td>cnt_Z[19]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R8C11[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[19]/Q</td>
</tr>
<tr>
<td>5.636</td>
<td>0.808</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[3][A]</td>
<td>un1_cntlto22_4_3_cZ/I1</td>
</tr>
<tr>
<td>6.668</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R9C12[3][A]</td>
<td style=" background: #97FFFF;">un1_cntlto22_4_3_cZ/F</td>
</tr>
<tr>
<td>7.503</td>
<td>0.835</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C12[1][B]</td>
<td>un1_cntlto24_d_0_cZ/I3</td>
</tr>
<tr>
<td>8.535</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>6</td>
<td>R11C12[1][B]</td>
<td style=" background: #97FFFF;">un1_cntlto24_d_0_cZ/F</td>
</tr>
<tr>
<td>8.551</td>
<td>0.016</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C12[2][B]</td>
<td>un1_cntlto24_d_cZ/I3</td>
</tr>
<tr>
<td>9.650</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R11C12[2][B]</td>
<td style=" background: #97FFFF;">un1_cntlto24_d_cZ/F</td>
</tr>
<tr>
<td>10.466</td>
<td>0.815</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C12[0][A]</td>
<td>cnt_RNO[20]/I3</td>
</tr>
<tr>
<td>11.498</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C12[0][A]</td>
<td style=" background: #97FFFF;">cnt_RNO[20]/F</td>
</tr>
<tr>
<td>11.498</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C12[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[20]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C12[0][A]</td>
<td>cnt_Z[20]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[20]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C12[0][A]</td>
<td>cnt_Z[20]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.195, 58.854%; route: 2.475, 34.716%; tC2Q: 0.458, 6.430%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.466</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.303</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[19]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[22]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[0][B]</td>
<td>cnt_Z[19]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R8C11[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[19]/Q</td>
</tr>
<tr>
<td>5.636</td>
<td>0.808</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[3][A]</td>
<td>un1_cntlto22_4_3_cZ/I1</td>
</tr>
<tr>
<td>6.668</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R9C12[3][A]</td>
<td style=" background: #97FFFF;">un1_cntlto22_4_3_cZ/F</td>
</tr>
<tr>
<td>7.503</td>
<td>0.835</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C12[1][B]</td>
<td>un1_cntlto24_d_0_cZ/I3</td>
</tr>
<tr>
<td>8.535</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>6</td>
<td>R11C12[1][B]</td>
<td style=" background: #97FFFF;">un1_cntlto24_d_0_cZ/F</td>
</tr>
<tr>
<td>8.551</td>
<td>0.016</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C12[2][B]</td>
<td>un1_cntlto24_d_cZ/I3</td>
</tr>
<tr>
<td>9.650</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R11C12[2][B]</td>
<td style=" background: #97FFFF;">un1_cntlto24_d_cZ/F</td>
</tr>
<tr>
<td>10.481</td>
<td>0.831</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C12[0][B]</td>
<td>cnt_RNO[22]/I3</td>
</tr>
<tr>
<td>11.303</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C12[0][B]</td>
<td style=" background: #97FFFF;">cnt_RNO[22]/F</td>
</tr>
<tr>
<td>11.303</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C12[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[22]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C12[0][B]</td>
<td>cnt_Z[22]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[22]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R8C12[0][B]</td>
<td>cnt_Z[22]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.985, 57.473%; route: 2.490, 35.917%; tC2Q: 0.458, 6.610%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.468</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.302</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[6]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[13]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C13[0][B]</td>
<td>cnt_Z[6]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R11C13[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[6]/Q</td>
</tr>
<tr>
<td>6.120</td>
<td>1.292</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[0][B]</td>
<td>un3_cnt_cry_6_0/I0</td>
</tr>
<tr>
<td>7.165</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_6_0/COUT</td>
</tr>
<tr>
<td>7.165</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[1][A]</td>
<td>un3_cnt_cry_7_0/CIN</td>
</tr>
<tr>
<td>7.222</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/COUT</td>
</tr>
<tr>
<td>7.222</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[1][B]</td>
<td>un3_cnt_cry_8_0/CIN</td>
</tr>
<tr>
<td>7.279</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_8_0/COUT</td>
</tr>
<tr>
<td>7.279</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[2][A]</td>
<td>un3_cnt_cry_9_0/CIN</td>
</tr>
<tr>
<td>7.336</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_9_0/COUT</td>
</tr>
<tr>
<td>7.336</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[2][B]</td>
<td>un3_cnt_cry_10_0/CIN</td>
</tr>
<tr>
<td>7.393</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_10_0/COUT</td>
</tr>
<tr>
<td>7.393</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C11[0][A]</td>
<td>un3_cnt_cry_11_0/CIN</td>
</tr>
<tr>
<td>7.450</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_11_0/COUT</td>
</tr>
<tr>
<td>7.450</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C11[0][B]</td>
<td>un3_cnt_cry_12_0/CIN</td>
</tr>
<tr>
<td>7.507</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_12_0/COUT</td>
</tr>
<tr>
<td>7.507</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C11[1][A]</td>
<td>un3_cnt_cry_13_0/CIN</td>
</tr>
<tr>
<td>8.070</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_13_0/SUM</td>
</tr>
<tr>
<td>8.891</td>
<td>0.821</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C11[2][A]</td>
<td>cnt_RNO_0[13]/I0</td>
</tr>
<tr>
<td>9.990</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C11[2][A]</td>
<td style=" background: #97FFFF;">cnt_RNO_0[13]/F</td>
</tr>
<tr>
<td>10.480</td>
<td>0.490</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C13[1][B]</td>
<td>cnt_RNO[13]/I2</td>
</tr>
<tr>
<td>11.302</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C13[1][B]</td>
<td style=" background: #97FFFF;">cnt_RNO[13]/F</td>
</tr>
<tr>
<td>11.302</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C13[1][B]</td>
<td style=" font-weight:bold;">cnt_Z[13]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C13[1][B]</td>
<td>cnt_Z[13]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[13]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C13[1][B]</td>
<td>cnt_Z[13]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>10</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.871, 55.840%; route: 2.603, 37.548%; tC2Q: 0.458, 6.612%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.478</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>11.291</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[3]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[14]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[2][A]</td>
<td>cnt_Z[3]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C9[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[3]/Q</td>
</tr>
<tr>
<td>5.167</td>
<td>0.339</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C9[3][B]</td>
<td>un1_cntlto10_N_4L5_cZ/I1</td>
</tr>
<tr>
<td>6.228</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R9C9[3][B]</td>
<td style=" background: #97FFFF;">un1_cntlto10_N_4L5_cZ/F</td>
</tr>
<tr>
<td>6.647</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[3][A]</td>
<td>un1_cntlto10/I3</td>
</tr>
<tr>
<td>7.469</td>
<td>0.822</td>
<td>tINS</td>
<td>RF</td>
<td>3</td>
<td>R9C10[3][A]</td>
<td style=" background: #97FFFF;">un1_cntlto10/F</td>
</tr>
<tr>
<td>8.453</td>
<td>0.984</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C12[0][A]</td>
<td>un1_cntlto14/I0</td>
</tr>
<tr>
<td>9.275</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R11C12[0][A]</td>
<td style=" background: #97FFFF;">un1_cntlto14/F</td>
</tr>
<tr>
<td>10.259</td>
<td>0.985</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C13[0][A]</td>
<td>cnt_RNO[14]/I0</td>
</tr>
<tr>
<td>11.291</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C13[0][A]</td>
<td style=" background: #97FFFF;">cnt_RNO[14]/F</td>
</tr>
<tr>
<td>11.291</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C13[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[14]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C13[0][A]</td>
<td>cnt_Z[14]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[14]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C13[0][A]</td>
<td>cnt_Z[14]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.737, 53.991%; route: 2.726, 39.388%; tC2Q: 0.458, 6.622%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.913</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.857</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[19]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[12]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[0][B]</td>
<td>cnt_Z[19]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R8C11[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[19]/Q</td>
</tr>
<tr>
<td>5.636</td>
<td>0.808</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[3][A]</td>
<td>un1_cntlto22_4_3_cZ/I1</td>
</tr>
<tr>
<td>6.668</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R9C12[3][A]</td>
<td style=" background: #97FFFF;">un1_cntlto22_4_3_cZ/F</td>
</tr>
<tr>
<td>7.503</td>
<td>0.835</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C12[1][B]</td>
<td>un1_cntlto24_d_0_cZ/I3</td>
</tr>
<tr>
<td>8.535</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>6</td>
<td>R11C12[1][B]</td>
<td style=" background: #97FFFF;">un1_cntlto24_d_0_cZ/F</td>
</tr>
<tr>
<td>8.551</td>
<td>0.016</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C12[2][B]</td>
<td>un1_cntlto24_d_cZ/I3</td>
</tr>
<tr>
<td>9.612</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>5</td>
<td>R11C12[2][B]</td>
<td style=" background: #97FFFF;">un1_cntlto24_d_cZ/F</td>
</tr>
<tr>
<td>10.035</td>
<td>0.423</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C11[1][A]</td>
<td>cnt_RNO[12]/I3</td>
</tr>
<tr>
<td>10.857</td>
<td>0.822</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R11C11[1][A]</td>
<td style=" background: #97FFFF;">cnt_RNO[12]/F</td>
</tr>
<tr>
<td>10.857</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C11[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[12]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C11[1][A]</td>
<td>cnt_Z[12]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[12]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C11[1][A]</td>
<td>cnt_Z[12]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.947, 60.842%; route: 2.082, 32.093%; tC2Q: 0.458, 7.065%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.290</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.836</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.126</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[3]</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_spi_Z</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[2][A]</td>
<td>cnt_Z[3]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C9[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[3]/Q</td>
</tr>
<tr>
<td>5.167</td>
<td>0.339</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C9[3][B]</td>
<td>un1_cntlto10_N_4L5_cZ/I1</td>
</tr>
<tr>
<td>6.228</td>
<td>1.061</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R9C9[3][B]</td>
<td style=" background: #97FFFF;">un1_cntlto10_N_4L5_cZ/F</td>
</tr>
<tr>
<td>6.647</td>
<td>0.419</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[3][A]</td>
<td>un1_cntlto10/I3</td>
</tr>
<tr>
<td>7.469</td>
<td>0.822</td>
<td>tINS</td>
<td>RF</td>
<td>3</td>
<td>R9C10[3][A]</td>
<td style=" background: #97FFFF;">un1_cntlto10/F</td>
</tr>
<tr>
<td>8.453</td>
<td>0.984</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C12[3][A]</td>
<td>un1_cntlto17_0_0_1_cZ/I1</td>
</tr>
<tr>
<td>9.275</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R11C12[3][A]</td>
<td style=" background: #97FFFF;">un1_cntlto17_0_0_1_cZ/F</td>
</tr>
<tr>
<td>9.286</td>
<td>0.011</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C12[0][B]</td>
<td>clk_spi_RNO/I1</td>
</tr>
<tr>
<td>10.088</td>
<td>0.802</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R11C12[0][B]</td>
<td style=" background: #97FFFF;">clk_spi_RNO/F</td>
</tr>
<tr>
<td>10.836</td>
<td>0.749</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C11[0][A]</td>
<td style=" font-weight:bold;">clk_spi_Z/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C11[0][A]</td>
<td>clk_spi_Z/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>clk_spi_Z</td>
</tr>
<tr>
<td>14.126</td>
<td>-0.043</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C11[0][A]</td>
<td>clk_spi_Z</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.507, 54.234%; route: 2.501, 38.678%; tC2Q: 0.458, 7.088%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.130</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.640</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[6]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[23]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C13[0][B]</td>
<td>cnt_Z[6]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R11C13[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[6]/Q</td>
</tr>
<tr>
<td>6.120</td>
<td>1.292</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[0][B]</td>
<td>un3_cnt_cry_6_0/I0</td>
</tr>
<tr>
<td>7.165</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_6_0/COUT</td>
</tr>
<tr>
<td>7.165</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[1][A]</td>
<td>un3_cnt_cry_7_0/CIN</td>
</tr>
<tr>
<td>7.222</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/COUT</td>
</tr>
<tr>
<td>7.222</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[1][B]</td>
<td>un3_cnt_cry_8_0/CIN</td>
</tr>
<tr>
<td>7.279</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_8_0/COUT</td>
</tr>
<tr>
<td>7.279</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[2][A]</td>
<td>un3_cnt_cry_9_0/CIN</td>
</tr>
<tr>
<td>7.336</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_9_0/COUT</td>
</tr>
<tr>
<td>7.336</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[2][B]</td>
<td>un3_cnt_cry_10_0/CIN</td>
</tr>
<tr>
<td>7.393</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_10_0/COUT</td>
</tr>
<tr>
<td>7.393</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C11[0][A]</td>
<td>un3_cnt_cry_11_0/CIN</td>
</tr>
<tr>
<td>7.450</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_11_0/COUT</td>
</tr>
<tr>
<td>7.450</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C11[0][B]</td>
<td>un3_cnt_cry_12_0/CIN</td>
</tr>
<tr>
<td>7.507</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_12_0/COUT</td>
</tr>
<tr>
<td>7.507</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C11[1][A]</td>
<td>un3_cnt_cry_13_0/CIN</td>
</tr>
<tr>
<td>7.564</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_13_0/COUT</td>
</tr>
<tr>
<td>7.564</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C11[1][B]</td>
<td>un3_cnt_cry_14_0/CIN</td>
</tr>
<tr>
<td>7.621</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_14_0/COUT</td>
</tr>
<tr>
<td>7.621</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C11[2][A]</td>
<td>un3_cnt_cry_15_0/CIN</td>
</tr>
<tr>
<td>7.678</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_15_0/COUT</td>
</tr>
<tr>
<td>7.678</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C11[2][B]</td>
<td>un3_cnt_cry_16_0/CIN</td>
</tr>
<tr>
<td>7.735</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_16_0/COUT</td>
</tr>
<tr>
<td>7.735</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C12[0][A]</td>
<td>un3_cnt_cry_17_0/CIN</td>
</tr>
<tr>
<td>7.792</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_17_0/COUT</td>
</tr>
<tr>
<td>7.792</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C12[0][B]</td>
<td>un3_cnt_cry_18_0/CIN</td>
</tr>
<tr>
<td>7.849</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C12[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_18_0/COUT</td>
</tr>
<tr>
<td>7.849</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C12[1][A]</td>
<td>un3_cnt_cry_19_0/CIN</td>
</tr>
<tr>
<td>7.906</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C12[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_19_0/COUT</td>
</tr>
<tr>
<td>7.906</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C12[1][B]</td>
<td>un3_cnt_cry_20_0/CIN</td>
</tr>
<tr>
<td>7.963</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C12[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_20_0/COUT</td>
</tr>
<tr>
<td>7.963</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C12[2][A]</td>
<td>un3_cnt_cry_21_0/CIN</td>
</tr>
<tr>
<td>8.020</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C12[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_21_0/COUT</td>
</tr>
<tr>
<td>8.020</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C12[2][B]</td>
<td>un3_cnt_cry_22_0/CIN</td>
</tr>
<tr>
<td>8.077</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C12[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_22_0/COUT</td>
</tr>
<tr>
<td>8.077</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C13[0][A]</td>
<td>un3_cnt_cry_23_0/CIN</td>
</tr>
<tr>
<td>8.640</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C13[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_23_0/SUM</td>
</tr>
<tr>
<td>8.640</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[23]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C13[0][A]</td>
<td>cnt_Z[23]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[23]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C13[0][A]</td>
<td>cnt_Z[23]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>18</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.520, 59.011%; route: 1.292, 30.257%; tC2Q: 0.458, 10.733%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.472</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.298</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[6]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[17]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C13[0][B]</td>
<td>cnt_Z[6]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R11C13[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[6]/Q</td>
</tr>
<tr>
<td>6.120</td>
<td>1.292</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[0][B]</td>
<td>un3_cnt_cry_6_0/I0</td>
</tr>
<tr>
<td>7.165</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_6_0/COUT</td>
</tr>
<tr>
<td>7.165</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[1][A]</td>
<td>un3_cnt_cry_7_0/CIN</td>
</tr>
<tr>
<td>7.222</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/COUT</td>
</tr>
<tr>
<td>7.222</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[1][B]</td>
<td>un3_cnt_cry_8_0/CIN</td>
</tr>
<tr>
<td>7.279</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_8_0/COUT</td>
</tr>
<tr>
<td>7.279</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[2][A]</td>
<td>un3_cnt_cry_9_0/CIN</td>
</tr>
<tr>
<td>7.336</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_9_0/COUT</td>
</tr>
<tr>
<td>7.336</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[2][B]</td>
<td>un3_cnt_cry_10_0/CIN</td>
</tr>
<tr>
<td>7.393</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_10_0/COUT</td>
</tr>
<tr>
<td>7.393</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C11[0][A]</td>
<td>un3_cnt_cry_11_0/CIN</td>
</tr>
<tr>
<td>7.450</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_11_0/COUT</td>
</tr>
<tr>
<td>7.450</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C11[0][B]</td>
<td>un3_cnt_cry_12_0/CIN</td>
</tr>
<tr>
<td>7.507</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_12_0/COUT</td>
</tr>
<tr>
<td>7.507</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C11[1][A]</td>
<td>un3_cnt_cry_13_0/CIN</td>
</tr>
<tr>
<td>7.564</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_13_0/COUT</td>
</tr>
<tr>
<td>7.564</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C11[1][B]</td>
<td>un3_cnt_cry_14_0/CIN</td>
</tr>
<tr>
<td>7.621</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_14_0/COUT</td>
</tr>
<tr>
<td>7.621</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C11[2][A]</td>
<td>un3_cnt_cry_15_0/CIN</td>
</tr>
<tr>
<td>7.678</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_15_0/COUT</td>
</tr>
<tr>
<td>7.678</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C11[2][B]</td>
<td>un3_cnt_cry_16_0/CIN</td>
</tr>
<tr>
<td>7.735</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_16_0/COUT</td>
</tr>
<tr>
<td>7.735</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C12[0][A]</td>
<td>un3_cnt_cry_17_0/CIN</td>
</tr>
<tr>
<td>8.298</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_17_0/SUM</td>
</tr>
<tr>
<td>8.298</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[17]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>cnt_Z[17]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[17]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>cnt_Z[17]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>12</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.178, 55.442%; route: 1.292, 32.891%; tC2Q: 0.458, 11.667%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.586</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.184</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[6]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[15]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C13[0][B]</td>
<td>cnt_Z[6]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R11C13[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[6]/Q</td>
</tr>
<tr>
<td>6.120</td>
<td>1.292</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[0][B]</td>
<td>un3_cnt_cry_6_0/I0</td>
</tr>
<tr>
<td>7.165</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_6_0/COUT</td>
</tr>
<tr>
<td>7.165</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[1][A]</td>
<td>un3_cnt_cry_7_0/CIN</td>
</tr>
<tr>
<td>7.222</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/COUT</td>
</tr>
<tr>
<td>7.222</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[1][B]</td>
<td>un3_cnt_cry_8_0/CIN</td>
</tr>
<tr>
<td>7.279</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_8_0/COUT</td>
</tr>
<tr>
<td>7.279</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[2][A]</td>
<td>un3_cnt_cry_9_0/CIN</td>
</tr>
<tr>
<td>7.336</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_9_0/COUT</td>
</tr>
<tr>
<td>7.336</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[2][B]</td>
<td>un3_cnt_cry_10_0/CIN</td>
</tr>
<tr>
<td>7.393</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_10_0/COUT</td>
</tr>
<tr>
<td>7.393</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C11[0][A]</td>
<td>un3_cnt_cry_11_0/CIN</td>
</tr>
<tr>
<td>7.450</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_11_0/COUT</td>
</tr>
<tr>
<td>7.450</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C11[0][B]</td>
<td>un3_cnt_cry_12_0/CIN</td>
</tr>
<tr>
<td>7.507</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_12_0/COUT</td>
</tr>
<tr>
<td>7.507</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C11[1][A]</td>
<td>un3_cnt_cry_13_0/CIN</td>
</tr>
<tr>
<td>7.564</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_13_0/COUT</td>
</tr>
<tr>
<td>7.564</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C11[1][B]</td>
<td>un3_cnt_cry_14_0/CIN</td>
</tr>
<tr>
<td>7.621</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_14_0/COUT</td>
</tr>
<tr>
<td>7.621</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C11[2][A]</td>
<td>un3_cnt_cry_15_0/CIN</td>
</tr>
<tr>
<td>8.184</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_15_0/SUM</td>
</tr>
<tr>
<td>8.184</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[15]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>cnt_Z[15]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[15]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>cnt_Z[15]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>10</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.064, 54.111%; route: 1.292, 33.874%; tC2Q: 0.458, 12.016%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.871</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.899</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[6]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[10]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C13[0][B]</td>
<td>cnt_Z[6]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R11C13[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[6]/Q</td>
</tr>
<tr>
<td>6.120</td>
<td>1.292</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[0][B]</td>
<td>un3_cnt_cry_6_0/I0</td>
</tr>
<tr>
<td>7.165</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_6_0/COUT</td>
</tr>
<tr>
<td>7.165</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[1][A]</td>
<td>un3_cnt_cry_7_0/CIN</td>
</tr>
<tr>
<td>7.222</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/COUT</td>
</tr>
<tr>
<td>7.222</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[1][B]</td>
<td>un3_cnt_cry_8_0/CIN</td>
</tr>
<tr>
<td>7.279</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_8_0/COUT</td>
</tr>
<tr>
<td>7.279</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[2][A]</td>
<td>un3_cnt_cry_9_0/CIN</td>
</tr>
<tr>
<td>7.336</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_9_0/COUT</td>
</tr>
<tr>
<td>7.336</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[2][B]</td>
<td>un3_cnt_cry_10_0/CIN</td>
</tr>
<tr>
<td>7.899</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_10_0/SUM</td>
</tr>
<tr>
<td>7.899</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C10[2][B]</td>
<td style=" font-weight:bold;">cnt_Z[10]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[2][B]</td>
<td>cnt_Z[10]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[10]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C10[2][B]</td>
<td>cnt_Z[10]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.779, 50.405%; route: 1.292, 36.609%; tC2Q: 0.458, 12.986%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.928</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.842</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[6]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[9]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C13[0][B]</td>
<td>cnt_Z[6]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R11C13[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[6]/Q</td>
</tr>
<tr>
<td>6.120</td>
<td>1.292</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[0][B]</td>
<td>un3_cnt_cry_6_0/I0</td>
</tr>
<tr>
<td>7.165</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_6_0/COUT</td>
</tr>
<tr>
<td>7.165</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[1][A]</td>
<td>un3_cnt_cry_7_0/CIN</td>
</tr>
<tr>
<td>7.222</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/COUT</td>
</tr>
<tr>
<td>7.222</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[1][B]</td>
<td>un3_cnt_cry_8_0/CIN</td>
</tr>
<tr>
<td>7.279</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_8_0/COUT</td>
</tr>
<tr>
<td>7.279</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[2][A]</td>
<td>un3_cnt_cry_9_0/CIN</td>
</tr>
<tr>
<td>7.842</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_9_0/SUM</td>
</tr>
<tr>
<td>7.842</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C10[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[9]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[2][A]</td>
<td>cnt_Z[9]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[9]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C10[2][A]</td>
<td>cnt_Z[9]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.722, 49.591%; route: 1.292, 37.210%; tC2Q: 0.458, 13.199%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.985</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.785</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[6]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[8]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C13[0][B]</td>
<td>cnt_Z[6]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R11C13[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[6]/Q</td>
</tr>
<tr>
<td>6.120</td>
<td>1.292</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[0][B]</td>
<td>un3_cnt_cry_6_0/I0</td>
</tr>
<tr>
<td>7.165</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_6_0/COUT</td>
</tr>
<tr>
<td>7.165</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[1][A]</td>
<td>un3_cnt_cry_7_0/CIN</td>
</tr>
<tr>
<td>7.222</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/COUT</td>
</tr>
<tr>
<td>7.222</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[1][B]</td>
<td>un3_cnt_cry_8_0/CIN</td>
</tr>
<tr>
<td>7.785</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_8_0/SUM</td>
</tr>
<tr>
<td>7.785</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C10[1][B]</td>
<td style=" font-weight:bold;">cnt_Z[8]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[1][B]</td>
<td>cnt_Z[8]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[8]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C10[1][B]</td>
<td>cnt_Z[8]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.665, 48.750%; route: 1.292, 37.831%; tC2Q: 0.458, 13.420%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.042</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.728</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[6]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[7]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C13[0][B]</td>
<td>cnt_Z[6]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R11C13[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[6]/Q</td>
</tr>
<tr>
<td>6.120</td>
<td>1.292</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[0][B]</td>
<td>un3_cnt_cry_6_0/I0</td>
</tr>
<tr>
<td>7.165</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_6_0/COUT</td>
</tr>
<tr>
<td>7.165</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[1][A]</td>
<td>un3_cnt_cry_7_0/CIN</td>
</tr>
<tr>
<td>7.728</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/SUM</td>
</tr>
<tr>
<td>7.728</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C10[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[7]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[1][A]</td>
<td>cnt_Z[7]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[7]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C10[1][A]</td>
<td>cnt_Z[7]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.608, 47.880%; route: 1.292, 38.473%; tC2Q: 0.458, 13.647%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.818</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.952</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[1]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[5]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[1][A]</td>
<td>cnt_Z[1]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C9[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[1]/Q</td>
</tr>
<tr>
<td>5.173</td>
<td>0.345</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C9[1][A]</td>
<td>un3_cnt_cry_1_0/I0</td>
</tr>
<tr>
<td>6.218</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C9[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_1_0/COUT</td>
</tr>
<tr>
<td>6.218</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C9[1][B]</td>
<td>un3_cnt_cry_2_0/CIN</td>
</tr>
<tr>
<td>6.275</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C9[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_2_0/COUT</td>
</tr>
<tr>
<td>6.275</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C9[2][A]</td>
<td>un3_cnt_cry_3_0/CIN</td>
</tr>
<tr>
<td>6.332</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C9[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_3_0/COUT</td>
</tr>
<tr>
<td>6.332</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C9[2][B]</td>
<td>un3_cnt_cry_4_0/CIN</td>
</tr>
<tr>
<td>6.389</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C9[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_4_0/COUT</td>
</tr>
<tr>
<td>6.389</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[0][A]</td>
<td>un3_cnt_cry_5_0/CIN</td>
</tr>
<tr>
<td>6.952</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_5_0/SUM</td>
</tr>
<tr>
<td>6.952</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C10[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[5]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[0][A]</td>
<td>cnt_Z[5]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[5]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C10[0][A]</td>
<td>cnt_Z[5]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.779, 68.899%; route: 0.345, 13.351%; tC2Q: 0.458, 17.751%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.875</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.895</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[1]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[4]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[1][A]</td>
<td>cnt_Z[1]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C9[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[1]/Q</td>
</tr>
<tr>
<td>5.173</td>
<td>0.345</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C9[1][A]</td>
<td>un3_cnt_cry_1_0/I0</td>
</tr>
<tr>
<td>6.218</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C9[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_1_0/COUT</td>
</tr>
<tr>
<td>6.218</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C9[1][B]</td>
<td>un3_cnt_cry_2_0/CIN</td>
</tr>
<tr>
<td>6.275</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C9[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_2_0/COUT</td>
</tr>
<tr>
<td>6.275</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C9[2][A]</td>
<td>un3_cnt_cry_3_0/CIN</td>
</tr>
<tr>
<td>6.332</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C9[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_3_0/COUT</td>
</tr>
<tr>
<td>6.332</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C9[2][B]</td>
<td>un3_cnt_cry_4_0/CIN</td>
</tr>
<tr>
<td>6.895</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C9[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_4_0/SUM</td>
</tr>
<tr>
<td>6.895</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C9[2][B]</td>
<td style=" font-weight:bold;">cnt_Z[4]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[2][B]</td>
<td>cnt_Z[4]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[4]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C9[2][B]</td>
<td>cnt_Z[4]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.722, 68.197%; route: 0.345, 13.652%; tC2Q: 0.458, 18.151%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.932</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.838</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[1]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[3]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[1][A]</td>
<td>cnt_Z[1]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C9[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[1]/Q</td>
</tr>
<tr>
<td>5.173</td>
<td>0.345</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C9[1][A]</td>
<td>un3_cnt_cry_1_0/I0</td>
</tr>
<tr>
<td>6.218</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C9[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_1_0/COUT</td>
</tr>
<tr>
<td>6.218</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C9[1][B]</td>
<td>un3_cnt_cry_2_0/CIN</td>
</tr>
<tr>
<td>6.275</td>
<td>0.057</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C9[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_2_0/COUT</td>
</tr>
<tr>
<td>6.275</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C9[2][A]</td>
<td>un3_cnt_cry_3_0/CIN</td>
</tr>
<tr>
<td>6.838</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C9[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_3_0/SUM</td>
</tr>
<tr>
<td>6.838</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C9[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[3]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[2][A]</td>
<td>cnt_Z[3]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[3]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C9[2][A]</td>
<td>cnt_Z[3]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>3</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.665, 67.462%; route: 0.345, 13.967%; tC2Q: 0.458, 18.571%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.987</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.783</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[24]</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_spi_Z</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[0][A]</td>
<td>cnt_Z[24]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>15</td>
<td>R8C11[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[24]/Q</td>
</tr>
<tr>
<td>5.684</td>
<td>0.856</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C11[0][A]</td>
<td>clk_spi_ldmx_cZ/I1</td>
</tr>
<tr>
<td>6.783</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C11[0][A]</td>
<td style=" background: #97FFFF;">clk_spi_ldmx_cZ/F</td>
</tr>
<tr>
<td>6.783</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C11[0][A]</td>
<td style=" font-weight:bold;">clk_spi_Z/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C11[0][A]</td>
<td>clk_spi_Z/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>clk_spi_Z</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C11[0][A]</td>
<td>clk_spi_Z</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.099, 45.545%; route: 0.856, 35.460%; tC2Q: 0.458, 18.995%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.989</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.781</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.770</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[1]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[2]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>4.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[1][A]</td>
<td>cnt_Z[1]/CLK</td>
</tr>
<tr>
<td>4.828</td>
<td>0.458</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C9[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[1]/Q</td>
</tr>
<tr>
<td>5.173</td>
<td>0.345</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C9[1][A]</td>
<td>un3_cnt_cry_1_0/I0</td>
</tr>
<tr>
<td>6.218</td>
<td>1.045</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C9[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_1_0/COUT</td>
</tr>
<tr>
<td>6.218</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C9[1][B]</td>
<td>un3_cnt_cry_2_0/CIN</td>
</tr>
<tr>
<td>6.781</td>
<td>0.563</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C9[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_2_0/SUM</td>
</tr>
<tr>
<td>6.781</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C9[1][B]</td>
<td style=" font-weight:bold;">cnt_Z[2]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.982</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>14.370</td>
<td>3.388</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[1][B]</td>
<td>cnt_Z[2]/CLK</td>
</tr>
<tr>
<td>14.170</td>
<td>-0.200</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[2]</td>
</tr>
<tr>
<td>13.770</td>
<td>-0.400</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C9[1][B]</td>
<td>cnt_Z[2]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.608, 66.693%; route: 0.345, 14.297%; tC2Q: 0.458, 19.010%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.982, 22.470%; route: 3.388, 77.530%</td>
</tr>
</table>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.708</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.067</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>clk_spi_Z</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_spi_Z</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C11[0][A]</td>
<td>clk_spi_Z/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>98</td>
<td>R11C11[0][A]</td>
<td style=" font-weight:bold;">clk_spi_Z/Q</td>
</tr>
<tr>
<td>3.695</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C11[0][A]</td>
<td>clk_spi_ldmx_cZ/I0</td>
</tr>
<tr>
<td>4.067</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R11C11[0][A]</td>
<td style=" background: #97FFFF;">clk_spi_ldmx_cZ/F</td>
</tr>
<tr>
<td>4.067</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C11[0][A]</td>
<td style=" font-weight:bold;">clk_spi_Z/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C11[0][A]</td>
<td>clk_spi_Z/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>clk_spi_Z</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C11[0][A]</td>
<td>clk_spi_Z</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.711</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.071</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[24]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[24]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[0][A]</td>
<td>cnt_Z[24]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>15</td>
<td>R8C11[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[24]/Q</td>
</tr>
<tr>
<td>3.699</td>
<td>0.006</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[0][A]</td>
<td>cnt_RNO[24]/I2</td>
</tr>
<tr>
<td>4.071</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R8C11[0][A]</td>
<td style=" background: #97FFFF;">cnt_RNO[24]/F</td>
</tr>
<tr>
<td>4.071</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C11[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[24]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[0][A]</td>
<td>cnt_Z[24]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[24]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R8C11[0][A]</td>
<td>cnt_Z[24]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.853</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.212</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[8]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[8]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[1][B]</td>
<td>cnt_Z[8]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R9C10[1][B]</td>
<td style=" font-weight:bold;">cnt_Z[8]/Q</td>
</tr>
<tr>
<td>3.695</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R9C10[1][B]</td>
<td>un3_cnt_cry_8_0/I0</td>
</tr>
<tr>
<td>4.212</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R9C10[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_8_0/SUM</td>
</tr>
<tr>
<td>4.212</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C10[1][B]</td>
<td style=" font-weight:bold;">cnt_Z[8]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[1][B]</td>
<td>cnt_Z[8]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[8]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C10[1][B]</td>
<td>cnt_Z[8]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.853</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.212</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[0]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[0]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[0][B]</td>
<td>cnt_Z[0]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R9C9[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[0]/Q</td>
</tr>
<tr>
<td>3.695</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R9C9[0][B]</td>
<td>un3_cnt_cry_0_0/I0</td>
</tr>
<tr>
<td>4.212</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R9C9[0][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_0_0/SUM</td>
</tr>
<tr>
<td>4.212</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C9[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[0]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[0][B]</td>
<td>cnt_Z[0]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[0]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C9[0][B]</td>
<td>cnt_Z[0]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.853</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.212</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[2]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[2]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[1][B]</td>
<td>cnt_Z[2]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R9C9[1][B]</td>
<td style=" font-weight:bold;">cnt_Z[2]/Q</td>
</tr>
<tr>
<td>3.695</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R9C9[1][B]</td>
<td>un3_cnt_cry_2_0/I0</td>
</tr>
<tr>
<td>4.212</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R9C9[1][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_2_0/SUM</td>
</tr>
<tr>
<td>4.212</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C9[1][B]</td>
<td style=" font-weight:bold;">cnt_Z[2]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[1][B]</td>
<td>cnt_Z[2]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[2]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C9[1][B]</td>
<td>cnt_Z[2]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.964</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.323</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[24]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[20]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[0][A]</td>
<td>cnt_Z[24]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RF</td>
<td>15</td>
<td>R8C11[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[24]/Q</td>
</tr>
<tr>
<td>3.951</td>
<td>0.258</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C12[0][A]</td>
<td>cnt_RNO[20]/I2</td>
</tr>
<tr>
<td>4.323</td>
<td>0.372</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C12[0][A]</td>
<td style=" background: #97FFFF;">cnt_RNO[20]/F</td>
</tr>
<tr>
<td>4.323</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C12[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[20]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C12[0][A]</td>
<td>cnt_Z[20]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[20]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R8C12[0][A]</td>
<td>cnt_Z[20]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 38.607%; route: 0.258, 26.799%; tC2Q: 0.333, 34.594%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.964</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.323</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[24]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[22]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[0][A]</td>
<td>cnt_Z[24]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RF</td>
<td>15</td>
<td>R8C11[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[24]/Q</td>
</tr>
<tr>
<td>3.951</td>
<td>0.258</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C12[0][B]</td>
<td>cnt_RNO[22]/I2</td>
</tr>
<tr>
<td>4.323</td>
<td>0.372</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R8C12[0][B]</td>
<td style=" background: #97FFFF;">cnt_RNO[22]/F</td>
</tr>
<tr>
<td>4.323</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C12[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[22]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C12[0][B]</td>
<td>cnt_Z[22]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[22]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R8C12[0][B]</td>
<td>cnt_Z[22]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 38.607%; route: 0.258, 26.799%; tC2Q: 0.333, 34.594%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.085</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.444</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[10]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[10]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[2][B]</td>
<td>cnt_Z[10]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C10[2][B]</td>
<td style=" font-weight:bold;">cnt_Z[10]/Q</td>
</tr>
<tr>
<td>3.927</td>
<td>0.234</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C10[2][B]</td>
<td>un3_cnt_cry_10_0/I0</td>
</tr>
<tr>
<td>4.444</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C10[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_10_0/SUM</td>
</tr>
<tr>
<td>4.444</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C10[2][B]</td>
<td style=" font-weight:bold;">cnt_Z[10]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[2][B]</td>
<td>cnt_Z[10]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[10]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C10[2][B]</td>
<td>cnt_Z[10]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.658%; route: 0.234, 21.615%; tC2Q: 0.333, 30.727%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.085</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.444</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[4]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[4]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[2][B]</td>
<td>cnt_Z[4]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C9[2][B]</td>
<td style=" font-weight:bold;">cnt_Z[4]/Q</td>
</tr>
<tr>
<td>3.927</td>
<td>0.234</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R9C9[2][B]</td>
<td>un3_cnt_cry_4_0/I0</td>
</tr>
<tr>
<td>4.444</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C9[2][B]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_4_0/SUM</td>
</tr>
<tr>
<td>4.444</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C9[2][B]</td>
<td style=" font-weight:bold;">cnt_Z[4]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[2][B]</td>
<td>cnt_Z[4]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[4]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C9[2][B]</td>
<td>cnt_Z[4]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.658%; route: 0.234, 21.615%; tC2Q: 0.333, 30.727%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.088</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.447</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[5]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[5]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[0][A]</td>
<td>cnt_Z[5]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R9C10[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[5]/Q</td>
</tr>
<tr>
<td>3.930</td>
<td>0.238</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R9C10[0][A]</td>
<td>un3_cnt_cry_5_0/I0</td>
</tr>
<tr>
<td>4.447</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R9C10[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_5_0/SUM</td>
</tr>
<tr>
<td>4.447</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C10[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[5]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[0][A]</td>
<td>cnt_Z[5]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[5]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C10[0][A]</td>
<td>cnt_Z[5]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.522%; route: 0.238, 21.838%; tC2Q: 0.333, 30.640%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.088</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.447</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[15]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[15]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>cnt_Z[15]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R9C11[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[15]/Q</td>
</tr>
<tr>
<td>3.930</td>
<td>0.238</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R9C11[2][A]</td>
<td>un3_cnt_cry_15_0/I0</td>
</tr>
<tr>
<td>4.447</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_15_0/SUM</td>
</tr>
<tr>
<td>4.447</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[15]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>cnt_Z[15]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[15]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C11[2][A]</td>
<td>cnt_Z[15]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.522%; route: 0.238, 21.838%; tC2Q: 0.333, 30.640%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.088</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.447</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[9]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[9]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[2][A]</td>
<td>cnt_Z[9]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R9C10[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[9]/Q</td>
</tr>
<tr>
<td>3.930</td>
<td>0.238</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R9C10[2][A]</td>
<td>un3_cnt_cry_9_0/I0</td>
</tr>
<tr>
<td>4.447</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R9C10[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_9_0/SUM</td>
</tr>
<tr>
<td>4.447</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C10[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[9]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[2][A]</td>
<td>cnt_Z[9]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[9]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C10[2][A]</td>
<td>cnt_Z[9]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.522%; route: 0.238, 21.838%; tC2Q: 0.333, 30.640%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.088</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.447</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[3]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[3]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[2][A]</td>
<td>cnt_Z[3]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R9C9[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[3]/Q</td>
</tr>
<tr>
<td>3.930</td>
<td>0.238</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R9C9[2][A]</td>
<td>un3_cnt_cry_3_0/I0</td>
</tr>
<tr>
<td>4.447</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R9C9[2][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_3_0/SUM</td>
</tr>
<tr>
<td>4.447</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C9[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[3]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[2][A]</td>
<td>cnt_Z[3]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[3]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C9[2][A]</td>
<td>cnt_Z[3]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.522%; route: 0.238, 21.838%; tC2Q: 0.333, 30.640%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.093</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.452</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[7]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[7]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[1][A]</td>
<td>cnt_Z[7]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R9C10[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[7]/Q</td>
</tr>
<tr>
<td>3.935</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R9C10[1][A]</td>
<td>un3_cnt_cry_7_0/I0</td>
</tr>
<tr>
<td>4.452</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R9C10[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_7_0/SUM</td>
</tr>
<tr>
<td>4.452</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C10[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[7]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C10[1][A]</td>
<td>cnt_Z[7]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[7]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C10[1][A]</td>
<td>cnt_Z[7]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.304%; route: 0.243, 22.197%; tC2Q: 0.333, 30.499%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.093</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.452</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[1]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[1]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[1][A]</td>
<td>cnt_Z[1]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R9C9[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[1]/Q</td>
</tr>
<tr>
<td>3.935</td>
<td>0.243</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R9C9[1][A]</td>
<td>un3_cnt_cry_1_0/I0</td>
</tr>
<tr>
<td>4.452</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R9C9[1][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_1_0/SUM</td>
</tr>
<tr>
<td>4.452</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C9[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[1]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C9[1][A]</td>
<td>cnt_Z[1]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[1]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C9[1][A]</td>
<td>cnt_Z[1]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.304%; route: 0.243, 22.197%; tC2Q: 0.333, 30.499%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.094</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.453</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[17]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[17]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>cnt_Z[17]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R9C12[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[17]/Q</td>
</tr>
<tr>
<td>3.936</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R9C12[0][A]</td>
<td>un3_cnt_cry_17_0/I0</td>
</tr>
<tr>
<td>4.453</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_17_0/SUM</td>
</tr>
<tr>
<td>4.453</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[17]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>cnt_Z[17]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[17]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>cnt_Z[17]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.253%; route: 0.244, 22.281%; tC2Q: 0.333, 30.466%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.098</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.457</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[23]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[23]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C13[0][A]</td>
<td>cnt_Z[23]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R9C13[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[23]/Q</td>
</tr>
<tr>
<td>3.940</td>
<td>0.247</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R9C13[0][A]</td>
<td>un3_cnt_cry_23_0/I0</td>
</tr>
<tr>
<td>4.457</td>
<td>0.517</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R9C13[0][A]</td>
<td style=" background: #97FFFF;">un3_cnt_cry_23_0/SUM</td>
</tr>
<tr>
<td>4.457</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[23]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C13[0][A]</td>
<td>cnt_Z[23]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[23]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C13[0][A]</td>
<td>cnt_Z[23]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.517, 47.100%; route: 0.247, 22.532%; tC2Q: 0.333, 30.368%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.134</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.493</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[24]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[19]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[0][A]</td>
<td>cnt_Z[24]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RF</td>
<td>15</td>
<td>R8C11[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[24]/Q</td>
</tr>
<tr>
<td>3.937</td>
<td>0.244</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C11[0][B]</td>
<td>cnt_RNO[19]/I2</td>
</tr>
<tr>
<td>4.493</td>
<td>0.556</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R8C11[0][B]</td>
<td style=" background: #97FFFF;">cnt_RNO[19]/F</td>
</tr>
<tr>
<td>4.493</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[19]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[0][B]</td>
<td>cnt_Z[19]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[19]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R8C11[0][B]</td>
<td>cnt_Z[19]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.556, 49.051%; route: 0.244, 21.541%; tC2Q: 0.333, 29.407%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.609</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[23]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[12]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C13[0][A]</td>
<td>cnt_Z[23]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R9C13[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[23]/Q</td>
</tr>
<tr>
<td>4.237</td>
<td>0.545</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C11[1][A]</td>
<td>cnt_RNO[12]/I1</td>
</tr>
<tr>
<td>4.609</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R11C11[1][A]</td>
<td style=" background: #97FFFF;">cnt_RNO[12]/F</td>
</tr>
<tr>
<td>4.609</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C11[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[12]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C11[1][A]</td>
<td>cnt_Z[12]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[12]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C11[1][A]</td>
<td>cnt_Z[12]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.372, 29.760%; route: 0.545, 43.573%; tC2Q: 0.333, 26.667%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.724</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.083</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[23]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[14]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C13[0][A]</td>
<td>cnt_Z[23]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>13</td>
<td>R9C13[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[23]/Q</td>
</tr>
<tr>
<td>3.970</td>
<td>0.277</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C13[2][A]</td>
<td>cnt_RNO_0[14]/I1</td>
</tr>
<tr>
<td>4.526</td>
<td>0.556</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C13[2][A]</td>
<td style=" background: #97FFFF;">cnt_RNO_0[14]/F</td>
</tr>
<tr>
<td>4.527</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C13[0][A]</td>
<td>cnt_RNO[14]/I2</td>
</tr>
<tr>
<td>5.083</td>
<td>0.556</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C13[0][A]</td>
<td style=" background: #97FFFF;">cnt_RNO[14]/F</td>
</tr>
<tr>
<td>5.083</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C13[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[14]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C13[0][A]</td>
<td>cnt_Z[14]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[14]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C13[0][A]</td>
<td>cnt_Z[14]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.112, 64.498%; route: 0.279, 16.167%; tC2Q: 0.333, 19.334%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.806</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.166</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[17]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[21]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>cnt_Z[17]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R9C12[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[17]/Q</td>
</tr>
<tr>
<td>3.936</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[3][B]</td>
<td>un1_cntlto17_d_s/I1</td>
</tr>
<tr>
<td>4.538</td>
<td>0.602</td>
<td>tINS</td>
<td>RF</td>
<td>7</td>
<td>R9C12[3][B]</td>
<td style=" background: #97FFFF;">un1_cntlto17_d_s/F</td>
</tr>
<tr>
<td>4.794</td>
<td>0.255</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[2][A]</td>
<td>cnt_RNO[21]/I1</td>
</tr>
<tr>
<td>5.166</td>
<td>0.372</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C13[2][A]</td>
<td style=" background: #97FFFF;">cnt_RNO[21]/F</td>
</tr>
<tr>
<td>5.166</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[2][A]</td>
<td style=" font-weight:bold;">cnt_Z[21]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C13[2][A]</td>
<td>cnt_Z[21]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[21]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C13[2][A]</td>
<td>cnt_Z[21]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.974, 53.921%; route: 0.499, 27.625%; tC2Q: 0.333, 18.454%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.806</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.166</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[17]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[16]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>cnt_Z[17]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R9C12[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[17]/Q</td>
</tr>
<tr>
<td>3.936</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[3][B]</td>
<td>un1_cntlto17_d_s/I1</td>
</tr>
<tr>
<td>4.538</td>
<td>0.602</td>
<td>tINS</td>
<td>RF</td>
<td>7</td>
<td>R9C12[3][B]</td>
<td style=" background: #97FFFF;">un1_cntlto17_d_s/F</td>
</tr>
<tr>
<td>4.794</td>
<td>0.255</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[1][A]</td>
<td>cnt_RNO[16]/I1</td>
</tr>
<tr>
<td>5.166</td>
<td>0.372</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C13[1][A]</td>
<td style=" background: #97FFFF;">cnt_RNO[16]/F</td>
</tr>
<tr>
<td>5.166</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[1][A]</td>
<td style=" font-weight:bold;">cnt_Z[16]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C13[1][A]</td>
<td>cnt_Z[16]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[16]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C13[1][A]</td>
<td>cnt_Z[16]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.974, 53.921%; route: 0.499, 27.625%; tC2Q: 0.333, 18.454%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.806</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.166</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[17]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[18]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>cnt_Z[17]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R9C12[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[17]/Q</td>
</tr>
<tr>
<td>3.936</td>
<td>0.244</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[3][B]</td>
<td>un1_cntlto17_d_s/I1</td>
</tr>
<tr>
<td>4.538</td>
<td>0.602</td>
<td>tINS</td>
<td>RF</td>
<td>7</td>
<td>R9C12[3][B]</td>
<td style=" background: #97FFFF;">un1_cntlto17_d_s/F</td>
</tr>
<tr>
<td>4.794</td>
<td>0.255</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[1][B]</td>
<td>cnt_RNO[18]/I1</td>
</tr>
<tr>
<td>5.166</td>
<td>0.372</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C13[1][B]</td>
<td style=" background: #97FFFF;">cnt_RNO[18]/F</td>
</tr>
<tr>
<td>5.166</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[1][B]</td>
<td style=" font-weight:bold;">cnt_Z[18]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C13[1][B]</td>
<td>cnt_Z[18]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[18]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C13[1][B]</td>
<td>cnt_Z[18]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.974, 53.921%; route: 0.499, 27.625%; tC2Q: 0.333, 18.454%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.901</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.275</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.374</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[17]</td>
</tr>
<tr>
<td class="label">To</td>
<td>clk_spi_Z</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[0][A]</td>
<td>cnt_Z[17]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R9C12[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[17]/Q</td>
</tr>
<tr>
<td>3.959</td>
<td>0.266</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C12[1][A]</td>
<td>un1_cntlto17_c_cZ/I1</td>
</tr>
<tr>
<td>4.331</td>
<td>0.372</td>
<td>tINS</td>
<td>RF</td>
<td>3</td>
<td>R11C12[1][A]</td>
<td style=" background: #97FFFF;">un1_cntlto17_c_cZ/F</td>
</tr>
<tr>
<td>4.344</td>
<td>0.013</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C12[0][B]</td>
<td>clk_spi_RNO/I2</td>
</tr>
<tr>
<td>4.729</td>
<td>0.385</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R11C12[0][B]</td>
<td style=" background: #97FFFF;">clk_spi_RNO/F</td>
</tr>
<tr>
<td>5.275</td>
<td>0.546</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C11[0][A]</td>
<td style=" font-weight:bold;">clk_spi_Z/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C11[0][A]</td>
<td>clk_spi_Z/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>clk_spi_Z</td>
</tr>
<tr>
<td>3.374</td>
<td>0.015</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C11[0][A]</td>
<td>clk_spi_Z</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.757, 39.511%; route: 0.826, 43.091%; tC2Q: 0.333, 17.398%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.909</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.268</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>3.359</td>
</tr>
<tr>
<td class="label">From</td>
<td>cnt_Z[24]</td>
</tr>
<tr>
<td class="label">To</td>
<td>cnt_Z[6]</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>DEFAULT_CLK:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C11[0][A]</td>
<td>cnt_Z[24]/CLK</td>
</tr>
<tr>
<td>3.693</td>
<td>0.333</td>
<td>tC2Q</td>
<td>RR</td>
<td>15</td>
<td>R8C11[0][A]</td>
<td style=" font-weight:bold;">cnt_Z[24]/Q</td>
</tr>
<tr>
<td>4.542</td>
<td>0.849</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C13[0][B]</td>
<td>cnt_3_cZ[6]/I1</td>
</tr>
<tr>
<td>5.268</td>
<td>0.726</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R11C13[0][B]</td>
<td style=" background: #97FFFF;">cnt_3_cZ[6]/F</td>
</tr>
<tr>
<td>5.268</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C13[0][B]</td>
<td style=" font-weight:bold;">cnt_Z[6]/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>0.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>26</td>
<td>IOL3[B]</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>3.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C13[0][B]</td>
<td>cnt_Z[6]/CLK</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>cnt_Z[6]</td>
</tr>
<tr>
<td>3.359</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C13[0][B]</td>
<td>cnt_Z[6]</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.726, 38.038%; route: 0.849, 44.497%; tC2Q: 0.333, 17.465%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.844, 25.135%; route: 2.515, 74.865%</td>
</tr>
</table>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h4>No recovery paths to report!</h4>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h4>No removal paths to report!</h4>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h3>MPW1</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>cnt_Z[4]</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>cnt_Z[4]/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>cnt_Z[4]/CLK</td>
</tr>
</table>
<h3>MPW2</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>cnt_Z[2]</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>cnt_Z[2]/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>cnt_Z[2]/CLK</td>
</tr>
</table>
<h3>MPW3</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>cnt_Z[18]</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>cnt_Z[18]/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>cnt_Z[18]/CLK</td>
</tr>
</table>
<h3>MPW4</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>cnt_Z[10]</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>cnt_Z[10]/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>cnt_Z[10]/CLK</td>
</tr>
</table>
<h3>MPW5</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>cnt_Z[11]</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>cnt_Z[11]/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>cnt_Z[11]/CLK</td>
</tr>
</table>
<h3>MPW6</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>cnt_Z[19]</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>cnt_Z[19]/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>cnt_Z[19]/CLK</td>
</tr>
</table>
<h3>MPW7</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>cnt_Z[12]</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>cnt_Z[12]/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>cnt_Z[12]/CLK</td>
</tr>
</table>
<h3>MPW8</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>clk_spi_Z</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>clk_spi_Z/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>clk_spi_Z/CLK</td>
</tr>
</table>
<h3>MPW9</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>cnt_Z[13]</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>cnt_Z[13]/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>cnt_Z[13]/CLK</td>
</tr>
</table>
<h3>MPW10</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>2.329</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>3.579</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.250</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>DEFAULT_CLK</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>cnt_Z[20]</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>5.984</td>
<td>0.984</td>
<td>tINS</td>
<td>FF</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>9.780</td>
<td>3.796</td>
<td>tNET</td>
<td>FF</td>
<td>cnt_Z[20]/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>DEFAULT_CLK(clock)</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>clk_50M_ibuf/I</td>
</tr>
<tr>
<td>10.844</td>
<td>0.844</td>
<td>tINS</td>
<td>RR</td>
<td>clk_50M_ibuf/O</td>
</tr>
<tr>
<td>13.359</td>
<td>2.515</td>
<td>tNET</td>
<td>RR</td>
<td>cnt_Z[20]/CLK</td>
</tr>
</table>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
<tr>
<td>98</td>
<td>clk_spi</td>
<td>8.307</td>
<td>3.800</td>
</tr>
<tr>
<td>26</td>
<td>clk_50M_c</td>
<td>1.982</td>
<td>3.796</td>
</tr>
<tr>
<td>15</td>
<td>cnt[24]</td>
<td>3.249</td>
<td>1.340</td>
</tr>
<tr>
<td>13</td>
<td>cnt[23]</td>
<td>5.136</td>
<td>1.003</td>
</tr>
<tr>
<td>7</td>
<td>un1_cntlto17_d_out</td>
<td>3.214</td>
<td>0.842</td>
</tr>
<tr>
<td>6</td>
<td>un1_cntlto24_d_0</td>
<td>1.982</td>
<td>0.842</td>
</tr>
<tr>
<td>5</td>
<td>un1_cntlt15</td>
<td>2.066</td>
<td>1.330</td>
</tr>
<tr>
<td>5</td>
<td>un1_cntlto24_d</td>
<td>1.982</td>
<td>1.316</td>
</tr>
<tr>
<td>3</td>
<td>cnt[17]</td>
<td>3.562</td>
<td>0.493</td>
</tr>
<tr>
<td>3</td>
<td>cnt[20]</td>
<td>4.048</td>
<td>0.819</td>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R11C24</td>
<td>0.514</td>
</tr>
<tr>
<td>R11C25</td>
<td>0.417</td>
</tr>
<tr>
<td>R11C23</td>
<td>0.361</td>
</tr>
<tr>
<td>R12C24</td>
<td>0.319</td>
</tr>
<tr>
<td>R9C19</td>
<td>0.306</td>
</tr>
<tr>
<td>R9C20</td>
<td>0.292</td>
</tr>
<tr>
<td>R12C23</td>
<td>0.292</td>
</tr>
<tr>
<td>R11C27</td>
<td>0.292</td>
</tr>
<tr>
<td>R12C25</td>
<td>0.278</td>
</tr>
<tr>
<td>R9C12</td>
<td>0.278</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
</table>
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